Toshiba advances next generation ADAS that uses Cypress Semper fail-safe storage

Cypress Semiconductor announced Wednesday that Toshiba Electronic Devices & Storage Corporation has selected Cypress’ Semper NOR Flash for its next-generation Visconti line of automotive Advanced Driver Assistance Systems (ADAS). 

Architected with an embedded Arm Cortex-M0 processing core, the Semper family is purpose-built for demanding automotive environments where high-density and functional safety compliance are required. The Toshiba Visconti ADAS SoC is specifically targeted for key automobile makers working toward Autonomous Driving level 2.

The Cypress Semper NOR Flash family leads the industry in Functional Safety compliance and was the first flash to be designed specifically to meet the ISO26262 automotive functional safety standard, reaching ASIL-B compliancy. 

Semper NOR Flash also supports automotive temperatures up to +125°C (AEC-Q100 Grade 1) and meets the density and performance requirements for storage in ADAS applications through Autonomous Driving level 5.

“For the Toshiba Visconti5 ADAS SoC, it is critical that the integrated components selected for the design are field-proven, built to the highest standards of safety and reliability, and will have the endurance required for advanced ADAS applications,” said Takeshi Sugahara, Technology Executive of Toshiba Electronic Devices & Storage Corporation. “Cypress’ fail-safe storage solutions are a key to enable our Visconti5 platform to exceed our customers’ expectations and requirements for next-generation automotive designs.”

“Cypress is proud of its success in providing the world’s most advanced and reliable fail-safe storage products with integrated compute core and functional safety for automotive applications,” said Amr El-Ashmawi, vice president of marketing, Memory Products Division at Cypress. “As the world’s number one market share provider of automotive-grade flash, we look forward to continuing our collaborative work with Toshiba for delivering next-generation ADAS systems in this growing segment of the automotive market.”

Rambus achieves GDDR6 performance at 18 Gbps; aimed at AI, ML, data center, autonomous driving systems that need higher bandwidth memory

Rambus Inc. announced it has achieved 18 Gbps performance with the Rambus GDDR6 Memory PHY. Running at the industry’s fastest data rate of 18 Gbps, the Rambus GDDR6 PHY IP delivers peak performance four-to-five times faster than current DDR4 solutions and continues the company’s longstanding tradition of developing leading-edge products. 

The Rambus GDDR6 PHY pairs with the companion GDDR6 memory controller from the recent acquisition of Northwest Logic to provide a complete and optimized memory subsystem solution.

Increased data usage in applications such as artificial intelligence, machine learning, data center, networking and automotive systems is driving a need for higher bandwidth memory. The coming introduction of high-bandwidth 5G networks will exacerbate this challenge. 

Working closely with memory partners, the Rambus GDDR6 solution gives system designers more options in selecting the memory system that meets both their bandwidth and cost requirements.

Rambus GDDR6 PHY achieves high speed of up to 18 Gbps, delivering a maximum bandwidth of up to 72 GB/s; complete and optimized memory subsystem solution with companion GDDR6 memory controller; offers PCB and package design support – allowing customers to bring their high-speed designs to production; and provides access to Rambus system and SI/PI experts helping ASIC designers to ensure maximized signal and power integrity for devices and systems.

It also features LabStation development environment that enables quick system bring-up, characterization and debug, and supports high-performance applications including networking, data center, ADAS, machine learning and AI.

The Rambus GDDR6 PHY will be fully compliant to the JEDEC GDDR6 (JESD250) standard, supporting up to 16 Gbps per pin, and is available on TSMC 7nm process. The GDDR6 interface supports 2 channels, each with 16 bits for a total data width of 32 bits. 

With speeds up to 16 Gbps per pin, the Rambus GDDR6 PHY will offer a maximum bandwidth of up to 64 GB/s. This PHY will be available in advanced FinFET nodes for leading-edge customer integration. The Rambus system-aware design methodology used for IP Cores delivers a customer focused experience with improved time-to-market and first-time-right quality. 

Rambus offers flexible delivery of IP cores and will work directly with the customer to provide a full system signal and power integrity analysis, creating an optimized chip layout. In the end, the customer receives a hard macro solution with a full suite of test software for quick turn-on, characterization and debug.