Supermicro debuts server class edge systems for open 5G radio access network (RAN) offerings

Supermicro Computer announced new solutions for 5G cell tower deployments leveraging fully-configurable SuperServers based on second generation Intel Xeon Scalable processors, O-RAN compliant partner software, and ability to operate in harsh environments. These capabilities accelerate the mobile network evolution from proprietary hardware/software to open source software and disaggregated hardware for 5G installations. 

Supermicro's two new systems are its first servers for 5G, the Intelligent Edge, and other embedded applications to be based on second generation Intel Xeon processors. 

The E403-9P-FN2T is built for demanding environments and includes three PCI-E slots for GPU and FPGA accelerator cards. The compact 1U 1019P-FHN2T is ideal for controlled environments such as micro data centers and re-purposed central office locations and features two full-height full-length PCI-E slots.

With these expansion slots, Supermicro can provide real-time Edge AI inferencing via GPU cards, and accelerate 5G RAN software and open-standard site-to-site communication using the Intel FPGA Programmable Acceleration Card N3000. These new servers complement Supermicro's Xeon D-based 1019D and E403 models. 

Supermicro is developing IP65-rated protective enclosures to meet the needs of outdoor environments such as cell towers and microcell sites.

Supermicro is a market leader in delivering high-performance, power-efficient open hardware server platforms extending the data center level remote management to edge computing platforms, and has deep experience with virtualization and containers, including software such as Kubernetes and VMware. 

The 5G architecture is based on open hardware platforms connected by standardized interfaces, and virtualized network elements. Supermicro joined the O-RAN Alliance to help build a cloud-native, open 5G RAN architecture, and these solutions will concurrently support 4G as networks transition to 5G.

The 5G core network has moved to a virtualized model, which runs on data center hardware where Supermicro's Resource-Saving Architecture provides computing platforms such as the high-performance multi-node BigTwin and the high-density SuperBlade and MicroBlade products. These systems leverage shared cooling and efficient power, and feature a disaggregated structure to enable the latest upgrades without the wasteful rip-and-replace of entire server racks.

Intel releases tiny EMIB that assist chips to ‘talk’ with each other

Intel unveiled its Embedded Multi-die Interconnect Bridge (EMIBs) chips that speed the flow of data inside nearly 1 million laptops and field programmable gate array devices worldwide. That number will soon soar and include more products as EMIB technology enters the mainstream. 

EMIB is a cost-effective approach to in-package high density interconnect of heterogeneous chips. It delivers a complex multi-layered sliver of silicon no bigger than a grain of rice, and lets chips fling enormous quantities of data back and forth among adjoining chips at blinding speeds: several gigabytes per second.

The industry refers to this application as 2.5D package integration. Instead of using a large silicon interposer typically found in other 2.5D approaches, EMIB uses a very small bridge die, with multiple routing layers. This bridge die is embedded as part of the substrate fabrication process.

For example, Intel’s Ponte Vecchio processor, a general-purpose GPU the company unveiled this month, contains EMIB silicon.

To meet customers’ unique needs, this innovative technology allows chip architects to cobble together specialized chips faster than ever. And compared with an older, competing design called an interposer — in which chips inside a package sit atop what is essentially a single electronic baseboard, with each chip plugged into it — tiny, flexible, cost-effective EMIB silicon offers an 85 percent increase in bandwidth. That can make tech — laptop, server, 5G processor, graphics card— run faster, and next-generation EMIB could double or even triple that bandwidth.

The silicon interposer in a typical 2.5D package is a piece of silicon larger-than-all interconnecting die. In contrast, the silicon bridge is a small piece of silicon embedded only under the edges of two interconnecting die. This allows for most size die to be attached in multiple dimensions, eliminating additional physical constraints on heterogeneous die attachment within the theoretical limits.

The image shows a difficult yet desirable layout. The industry standard 2.5D solution cannot accommodate this, as the silicon interposer cannot be produced large enough to connect all the die. Yet EMIB allows for the flexibility in this die placement, allowing scaling in both dimensions.

Intel debuts GPU architecture with HPC and AI acceleration, and oneAPI software stack for heterogeneous architectures

Intel unveiled its vision for extending its leadership in the convergence of high-performance computing (HPC) and artificial intelligence (AI) with additions to its data-centric silicon portfolio and an ambitious new software initiative that represents a paradigm shift from single-architecture, single-vendor programming models.

Addressing the increasing use of heterogeneous architectures in high-performance computing, Intel expanded on its existing technology portfolio to move, store and process data more effectively by announcing a new category of discrete general-purpose GPUs optimized for AI and HPC convergence. 

Intel also launched the oneAPI industry initiative to deliver a unified and simplified programming model for application development across heterogenous processing architectures, including CPUs, GPUs, FPGAs and other accelerators. The launch of oneAPI represents millions of Intel engineering hours in software development and marks a game-changing evolution from limiting, proprietary programming approaches to an open standards-based model for cross-architecture developer engagement and innovation.

The oneAPI initiative Intel launched will define programming for an increasingly AI-infused, multi-architecture world. oneAPI delivers a unified and open programming experience to developers on the architecture of their choice without compromising performance and eliminating the complexity of separate code bases, multiple-programming languages, and different tools and workflows. oneAPI preserves existing software investments with support for existing languages, while delivering flexibility for developers to create versatile applications.

oneAPI includes both an industry initiative based on open specifications and an Intel beta product. The oneAPI specification includes a direct programming language, APIs and a low-level hardware interface. Intel’s oneAPI beta software provides developers a comprehensive portfolio of developer tools that include compilers, libraries and analyzers, packaged into domain-focused toolkits. 

The initial oneAPI beta release targets Intel Xeon scalable processors, Intel Core processors with integrated graphics, and Intel FPGAs, with additional hardware support to follow in future releases.

Aldec delivers comprehensive portfolio of FMC daughter cards

Aldec Inc., vendor of mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, expanded its  FPGA Mezzanine Card (FMC) product line to support various applications in the areas of IIoT, networking, embedded vision and automotive.

The FMC standard from ANSI/VITA has been a key enabler for extending I/O support for a range of applications.

Established in 1984, Aldec provides electronic design certification and offers a patented technology suite including RTL Design, RTL simulators, hardware-assisted verification, SoC and ASIC prototyping, design rule checking, CDC verification, IP cores, high-performance computing platforms, embedded development systems, requirements lifecycle management, DO-254 functional verification and military/aerospace solutions. 

“We now provide the most comprehensive portfolio of FMC daughter cards that can be used for FPGA development, ASIC emulation and prototyping,” said Zibi Zalewski, hardware division general manager. “Our FMC connectors are based on High Pin Count (HPC) type that is compliant with ANSI/VITA 57.1, and provides individual signaling speed of up to 25 Gb/s per link and overall bandwidth of 200 Gb/s between the daughter card and carrier card for selected configurations.”

The FMC daughter cards are compatible with TySOM FPGA development boards or HES ASIC emulation/prototyping boards.

BittWare expands line with multiple capabilities on FPGA acceleration products to address growing industry technology demands

BittWare, a Molex company, expanded on Tuesday its offerings and solutions to further address the growing need for computing technology. These BittWare offerings provide high-end, integrated solutions for memory bandwidth and advanced cooling, enabling customers to go to market faster.

BittWare’s broad range of compute-focused accelerator cards includes HBM2-enabled FPGAs from both Intel and Xilinx yielding up to 4Tbps of bandwidth. These Stratix-10 MX and Virtex UltraScale+ based products are now shipping with a choice of abstracted toolflows, including OpenCL. 

A new alternative to high-bandwidth memory implementation, on display at SC19, will be BittWare’s new S7t accelerator card developed in conjunction with Achronix Semiconductor. 

This product features the newly announced Achronix 7nm Speedster 7t FPGA, which offers a range of capabilities, including low-cost and highly flexible GDDR6 memories that deliver HBM-class memory bandwidth without the HBM, as well as a revolutionary 2D Network-on-Chip (NoC) for high bandwidth and energy-efficient data movement.

As customers push computing technology to new limits, there is a need to consider more advanced cooling options – even for energy-efficient accelerators such as FPGAs. At Supercomputing 2019, BittWare will present Achronix, Intel and Xilinx based FPGA accelerator cards featuring Direct Liquid Cooling (DLC) technology from CoolIT System. 

Data center managers are increasingly turning to liquid cooling as the most reliable and efficient cooling method. In comparison to air, liquid cooling is 2-10 times more effective in transporting heat away from a source to a secondary cooling surface.

BittWare’s range of certified TeraBox server platforms, targeting networking and HPC clusters feature the latest FPGA accelerators enabling customers to develop and deploy quicker, while reducing risk and total cost. This product range will be further extended with the introduction of the TeraBox 1400DN. 

This ultra-high density 1U server based on the DELL C4140 PowerEdge server features four double-width PCIe cards with front-panel access and dual Xeon Scalable CPUs. Customers can order the server with a choice of Achronix, Intel or Xilinx FPGA accelerators supporting a high density of network ports: four 400GbE, up to 128 10/25GbE or up to 32 100GbE.

BittWare, in conjunction with Eideticom, will be displaying the world’s first FPGA-based computational storage processor (CSP). This solution, based on the BittWare 250-U2 accelerator, adheres to the industry standard U.2 form factor allowing it to be front-servicable in standard rackmount chassis. 

When programmed with Eideticom’s NoLoad IP, each Computational Storage Service executed on the 250-U2 is presented to the host operating system as a regular NVMe Controller and binds to the standard NVMe driver. This avoids the need for customers to develop or use proprietary drivers or software stacks. Instead, customers can continue using their preferred Linux, Windows or VMWare operating systems and host-based applications.

“With FPGA-based acceleration achieving wider adoption, it is essential that there is a supplier who can deliver and support higher-quality volume deployments,” said Craig Petrie, vice president of marketing for BittWare. “Traditionally, FPGA card vendors have provided cutting-edge technology primarily to innovators and early adopters; it is quite a different challenge to implement the extensive qualification, validation, life cycle management and support required by the newer enterprise-class customers. BittWare, as a part of Molex, is in the unique position to drive technology advancements while simultaneously delivering enterprise-class product consistently at high run-rates. This powerful combination allows our customers to adopt the latest and greatest FPGAs at the card and server-level with reduced risk and cost.”

Accolade partners with Titan IC to boost acceleration on FPGA-based SmartNICs and ATLAS Packet conditioners

Titan IC announced on Monday a new licensing technology partnership with Accolade Technology, developer of FPGA-based SmartNICs and the ATLAS Series of Packet Conditioners. Accolade will license Titan IC’s RXP technology to accelerate complex searching and pattern matching required to deliver security solutions on their next generation SmartNIC and ATLAS platforms.

Searching large volumes of data at high speeds, the RXP hardware acceleration engine offloads processor-intensive search and analytics tasks from the host CPU, delivering search acceleration for a host of applications such as cybersecurity, Natural Language Processing (NLP), edge computing and computational storage.

Boston-based Accolade Technology will embed Titan IC’s 100Gbps RXP (Regular eXpression Processor) technology on their ANIC line of FPGA-based PCIe 1-100GE SmartNICs and ATLAS Packet Conditioners enabling line-speed processing on a host of network monitoring and cyber security applications.

Titan and Accolade will partner on delivering these solutions to both existing and new customers in the enterprise, telecom, defense and government markets.

Titan IC provides accelerated search and analytics within high-speed networks and big data worldwide. The company’s core technology, RXP, is regarded as the industry-standard for high-speed complex pattern matching, real-time Internet traffic inspection and the detection of strings, keywords and malware using regular expressions (RegEx). Licensed internationally for ASIC, SoC and FPGA designs, RXP can be found in the products of many leading vendors within the semiconductor, cybersecurity, government and data analytics markets.

As a hardware engine, RXP technology offloads RegEx processing, freeing up CPU cores and delivering faster throughput and increased efficiency for its customers. Its unique ability to handle combinations of high throughput, rule depth and complexity make it the perfect solution for a wide range of applications such as intrusion detection, deep packet inspection, SmartNIC, lawful interception, logfile analytics, in-storage search and many more.

Accolade delivers Intelligent 1-100GE FPGA-based host CPU offload PCIe SmartNICs and scalable ATLAS packet conditioners. Accolade's products and IP enables complete packet capture, deduplication, advanced packet parsing, flow shunting and packet filtering. Customers are vendors in network monitoring, cybersecurity, telecom infrastructure as well as test and measurement solutions. 

“The combination of RXP and the processing power of Accolade’s ANIC SmartNICs and Atlas Packet Conditioners creates a formidable host CPU offload solution for network monitoring and cyber security applications,” said Robbie Dhillon, CEO of Accolade. “Our strategic partnership with Titan IC will enable us to offer Accolade’s market leading SmartNICs and ATLAS Packet Conditioners to our collective customer base. As traffic volumes and throughput continues to scale, the addition of RXP as a key IP block on our SmartNIC and ATLAS products delivers significant value to our customers.”

“We are delighted to add Accolade Technology as the latest licensee of RXP and a valuable Strategic Technology Partner,” said Titan IC CEO, Noel McKenna. “RXP is fast becoming the defacto standard for search acceleration within SmartNIC devices as well as in the wider fields of cybersecurity, storage and big data analytics. Accolade’s range of ANIC SmartNIC and ATLAS Packet Conditioners are very well regarded throughout the industry and we strongly believe that RXP will play a key role in strengthening their market position.”

BittWare, Achronix introduce enterprise-class PCIe accelerator product featuring 7nm Speedster7t FPGA

BittWare, a Molex company, has collaborated with Achronix Semiconductor to introduce the S7t-VG6 PCIe accelerator product—a feature-rich PCIe card sporting the new Achronix 7nm Speedster7t FPGA. 

This next generation product offers a range of breakthrough capabilities including low-cost and highly flexible GDDR6 memories that offer HBM-class memory bandwidth, high-performance machine learning processors and a revolutionary 2D network-on-chip for high bandwidth and energy-efficient data movement.

The S7t-VG6 offers a 7nm Achronix FPGA that is optimized for high-speed networking and fast, high-capacity memory access. Featuring a QSFP-DD (double-density) cage, the board supports up to 1x 400GbE or 4x 100GbE using the 56G PAM4-enabled Speedster 7t device. 

An additional QSFP port supports 2x 100GbE, and a 4x OCuLink connector supports NVMe attached storage. Sixteen channels of GDDR6 graphics DRAM handle high-bandwidth memory requirements, providing up to 512GB/s.

The BittWare VectorPath accelerator card is designed for high-performance and high-bandwidth data applications and features 1x400GbE and 2x100GbE interfaces; 8 banks of GDDR6 memory with 4 Tbps aggregate bandwidth; 20 Tbps 2D Network-on-Chip (NoC); 1 bank of DDR4 running at 2666MHz with ECC; PCIe compliance and certification; and 692K 6-input LUTs.

This enterprise-class product leverages BittWare’s extensive experience designing, qualifying, deploying and supporting accelerator cards. Its features include choice of thermal cooling options: passive, active or liquid; comprehensive Board Management Controller (BMC); support for Linux and Windows operating systems; developer toolkit: API, PCIe drivers, application example designs and diagnostic self-test; and option to purchase the S7t pre-integrated as a DELL or HPE server from BittWare TeraBox range.

The initial S7t-VG6 shipments are scheduled to begin by the second quarter of next year. 

Renesas expands access of IP solutions including 7nm process TCAM, advanced standard Ethernet TSN IPs

Renesas Electronics announced expanded access to its highly sought portfolio of intellectual property (IP) licenses that allow designers to meet a broad range of customer requirements in a rapidly changing industry. Starting today, customers will have access to IPs such as advanced 7nm (nanometer) SRAM and TCAM, and standard Ethernet time-sensitive networking (TSN) IP. 

Furthermore, Renesas is working on providing a system IP which includes PIM (processing in memory), which attracted attention as an AI accelerator, presented in a conference paper in June 2019. With these IPs, customers can jump start their advanced semiconductor device development projects, such as the development of next-generation artificial intelligence (AI) chips or ASICs for 5G networks.

The Renesas accelerator is based on the processing-in-memory (PIM) architecture, an increasingly popular approach for AI technology, in which multiply-and-accumulate operations are performed in the memory circuit as data is read out from that memory.

Customers developing custom chips or using FPGA devices for early development can leverage Renesas IP in their subsystem design or speed up software development, respectively, allowing them to focus resources on their speciality areas, speed up the development process, and bring highly competitive products to market. 

Customers who prefer to use existing software assets can take advantage of Renesas IP assets to achieve more efficient system development by reducing the resources required to develop, verify, and evaluate software and boards.

To support customers’ semiconductor development efforts, Renesas has also established a network of partner companies ready to support users' unique needs. This network includes design houses that perform contract semiconductor design and technology partners who will provide an array of software and middleware tools. 

This network will accelerate users' technology innovations and product development efforts by lowering the barriers to entry for semiconductor device and FPGA development. Renesas can also introduce experienced users to model-based design development environments that fully utilize leading-edge IP.

In September 2018, Renesas opened its extensive IP license portfolio, offering access to more than 40 licenses, including CPU cores, timer IP for motor applications, USB cores, and SRAM. In 2019, Renesas received over 100 enquiries and have started supplying IPs to many users. Renesas aims to exceed IP sales annual market growth rate of 10 percent, and will expand the provision of IP and support system while creating new, and expanding old, IP markets.