Wind River announces RISC-V support for VxWorks RTOS

Wind River announced this week RISC-V open architecture support for its VxWorks real-time operating system (RTOS), which is a widely deployed commercial RTOS to have support for the RISC-V open hardware instruction set architecture (ISA). 

The company has also joined the RISC-V Foundation, a non-profit consortium chartered to standardize, protect, and promote RISC-V ISA together with its hardware and software ecosystem for use in all computing devices.

VxWorks is a deterministic, high-performance RTOS that sets the standard for a scalable, future-proof, secure, safe, and reliable operating environment for mission-critical devices and systems that must meet the highest standards.

VxWorks is ideal for hard real-time embedded applications because it is a deterministic, priority-based, preemptive RTOS with low latency and minimal jitter. In addition to standard preemption, VxWorks can ensure that safety- and time-critical applications get a predetermined number of CPU cycles through various forms of scheduling as well as time and space partitioning. It also provides flexible features needed for various industries. 

As new features and functionality are added to VxWorks, compatibility is always top of mind because Wind River strives to protect and future proof its customers’ software and tool investments. Compatibility allows developers to take advantage of the latest VxWorks innovation, enabling them to add new features and upgrades with minimal retesting of the entire system, thereby saving both project time and expense.

VxWorks has IPv4 and IPv6 stacks that are also time-sensitive networking (TSN) capable, guaranteeing real-time communications and packet delivery within a bounded time or latency on a switched Ethernet network. VxWorks supports industrial applications, including but not limited to OPC Unified Architecture (OPC UA); SocketCAN used in automotive applications; and host, target, and on-the-go (OTG) USB.

VxWorks supports 32- and 64-bit, as well as multi-core processors including Intel, Arm and Power Architecture. Its comprehensive multi-core processor support allows OS configurations for asymmetric multiprocessing (AMP) and for symmetric multiprocessing (SMP) with CPU affinity for bound multiprocessing (BMP). 

Adding RISC-V support for VxWorks comes on the heels of the recent wave of innovations made to the RTOS, making it the first to include support for C++17, Boost, Python, and the Rust collection of technologies.

“We are pleased to welcome Wind River into the RISC-V Foundation and our global ecosystem," said Calista Redmond, CEO of the RISC-V Foundation. “VxWorks significantly extends the reach of RISC-V in the embedded developer space. We look forward to continued software developments by Wind River and the RISC-V community.”

“It’s exciting to see RISC-V gain significant industry traction as it brings the dynamism of open architecture development to hardware,” said Michel Genard, vice president of product at Wind River. “Wind River is very pleased to continue innovating VxWorks while contributing to the success of RISC-V with collaborations like the ones we have with SiFive and MicroChip providing support for their Unleashed and PolarFire SoC FPGA boards.”

“Having VxWorks support for our RISC-V-based PolarFire SoC FPGA family brings an extremely compelling offering to embedded systems designers who increasingly need real-time, and Linux capable solutions that are low power, thermally efficient, and secure,” said Shakeel Peera, associate vice president, marketing, FPGA business unit at Microchip. “Our partnership with Wind River is an important one as we work together to advance the collaborative RISC-V ecosystem and community.”

“The adoption of RISC-V by Wind River in VxWorks is a great step in the ongoing enablement of the RISC-V ecosystem,” said Dr. Naveed Sherwani, president and CEO of SiFive. “The ability to run VxWorks on SiFive Core IP and devices will enable new application markets across the world.”

GigaSpaces Version 15.0 set to operationalize and optimize machine learning; gain actionable insights from data

GigaSpaces announced this week availability of GigaSpaces Version 15.0, including InsightEdge Platform and XAP, to operationalize and optimize machine learning with the required speed, scale, accuracy and management tools. GigaSpaces Version 15.0 powers machine learning operations (MLOps) initiatives, helping enterprises maximize the business value derived from big data. 

Deploying machine learning models in production remains a major challenge for many enterprises. The Gartner Accelerate Your Machine Learning and Artificial Intelligence Journey Using These DevOps Best Practices says that, “according to the 2019 Gartner CIO Survey, AI and ML continue to be viewed as the No. 1 game-changing technology by CIOs. However, most organizations underestimate how long it will take to move AI and ML projects into production.”

GigaSpaces delivers fast in-memory computing platforms for real-time insight to action and extreme transactional processing.  With GigaSpaces, enterprises can operationalize machine learning and transactional processing to gain real-time insights on their data and act upon them in the moment.  

The always-on platforms for mission-critical applications across cloud, on-premise or hybrid, are leveraged by organizations across various verticals, including financial services, retail, transportation, telecom and healthcare. GigaSpaces offices are located in the US, Europe and Asia.

GigaSpaces Version 15.0 simplifies integrating AI workloads with the organization’s core infrastructure, accelerating machine learning deployment and enabling enterprises to more readily experience the business benefits of machine learning models.

GigaSpaces Version 15.0 introduces a new enterprise-grade monitoring and administration tool, Ops Manager, that provides visibility into the components of systems running models including logs, inputs, outputs and exceptions, using different performance visualization techniques. 

The Ops Manager enables continuous monitoring of machine learning pipelines, starting at the cluster level and drilling through to individual services so users can maintain accurate data models and ensure that problems are resolved before they affect overall performance. 

The new AnalyticsXtreme Batch Indexing included in GigaSpaces InsightEdge Version 15.0 optimizes and automates data access and storage with the added ability to move data between the more frequent (cold data) access and infrequent (archive data) access tiers on data lakes and data warehouses.  

The performance of ML models is enhanced since frequently accessed cold data can be retrieved 80 times faster directly from data lakes and processing costs are reduced as data access patterns change. 

GigaSpaces Version 15.0 also provides a native smart space client in Kubernetes that supports remote CRUD operations, task execution, and event-driven analytics providing high throughput and fast serialization, as well as automatic load balancing. Writing and updating of data without a predefined schema allows easy changes to the data model, while ensuring compatibility with JDBC and BI tools so code can be integrated more reliably and faster with lower administrative overhead.

“Machine learning is becoming an essential component of mission critical applications to optimize operations and deliver superior real time customer experiences,” said Yoav Einav, VP product at GigaSpaces. “GigaSpaces Version 15.0 provides enterprises with the machine learning model management capabilities, speed and scale that they need to accelerate their machine learning and artificial intelligence journey.”

Microsoft Research Open Data Project lays down evolving standards for data access and reproducible research

Microsoft Research has announced that it will be adopting the Open Use of Data Agreement (O-UDA) data for several datasets that the company offers. 

The Open Use of Data Agreement (O-UDA) is intended to make it easier for individuals and organizations that want to share data to do so, with minimal requirements for users and no restrictions on use. The O-UDA is complemented by the Computational Use of Data Agreement (C-UDA), an agreement intended for situations where a specific data use scenario is desirable or required.

It is not appropriate for datasets that include any data that might include materials subject to privacy laws (such as the GDPR or HIPAA) or other unlicensed third-party materials. 

The O-UDA meets the open definition: it does not impose any restriction with respect to the use or modification of data other than ensuring that attribution and limitation of liability information is passed downstream. In the research context, this implies that users of the data need to cite the corresponding publication with which the data is associated. This aids in findability and reusability of data, an important tenet in the FAIR guiding principles for scientific data management and stewardship.

Microsoft recognizes that in certain cases, datasets useful for AI and research analysis may not be able to be fully “open” under the O-UDA. For example, they may contain third-party copyrighted materials, such as text snippets or images, from publicly available sources. 

The law permits their use for research, so following the principle that research data should be “as open as possible, as closed as necessary,” Microsoft developed the Computational Use of Data Agreement (C-UDA) to make data available for research while respecting other interests. The software giant will prefer the O-UDA where possible, but perceives the C-UDA as a useful tool for ensuring that researchers continue to have access to important and relevant datasets.

Microsoft researcher John Krumm and collaborators collected GPS data from 21 people who carried a GPS receiver in the Seattle area. Users who provided their data agreed to it being shared as long as certain geographic regions were deleted. 

This work covers key research on privacy preservation of GPS data as evidenced in the corresponding paper, “Exploring End User Preferences for Location Obfuscation, Location-Based Services, and the Value of Location,” which was accepted at the Twelfth ACM International Conference on Ubiquitous Computing (UbiComp 2010). The paper has been cited 147 times, including for research that builds upon this work to further the field of preservation of geo-privacy for location-based services providers.

Another example dataset is that of labeled hand images and video clips collected by researchers Eyal Krupka, Kfir Karmon, and others. The research addresses an important computer vision and machine learning problem that deals with developing a hand-gesture-based interface language. 

The data was recorded using depth cameras and has labels that cover joints and fingertips. The two datasets included are FingersData, which contains 3,500 labeled depth frames of various hand poses, and GestureClips, which contains 140 gesture clips (100 of these contain labeled hand gestures and 40 contain non-gesture activity). 

The research associated with this dataset is available in the paper “Toward Realistic Hands Gesture Interface: Keeping it Simple for Developers and Machines,” which was published in Proceedings of the 2017 CHI Conference on Human Factors in Computing Systems.

Finally, the FigureQA dataset generated by researchers Samira Ebrahimi Kahou, Adam Atkinson, Adam Trischler, Yoshua Bengio and collaborators, introduces a visual reasoning task for research that is specific to graphical plots and figures. 

Microsoft Research Open Data project was conceived from the start to reflect Microsoft Research’s commitment to fostering open science and research and to achieve this without compromising the ethics of collecting and sharing data. The company aims to make it easier for researchers to maintain provenance of data while having the ability to reference and build upon it.

Intel opposes Qualcomm’s appeal in US District Court; files brief supporting FTC

Intel files a brief supporting the Federal Trade Commission (FTC) and opposing Qualcomm’s appeal of the judgment rendered in May against Qualcomm by the United States District Court, Northern District of California. 

The District Court found that “Qualcomm’s licensing practices have strangled competition in the CDMA and premium LTE modem chip markets for years, and harmed rivals, OEMs and end consumers.” The District Court also found that Qualcomm’s conduct “unfairly tends to destroy competition itself.”

Intel agrees with the District Court’s findings. Intel suffered the brunt of Qualcomm’s anticompetitive behavior, was denied opportunities in the modem market, was prevented from making sales to customers and was forced to sell at prices artificially skewed by Qualcomm. 

Qualcomm would have you believe that its position in the market today — as the last surviving U.S. supplier of premium modem chips — is due to its “ingenuity and business acumen,” and that its rivals in the market failed simply because “they did not offer good enough chips at low enough prices.” This is simply not true.

Instead, as detailed in the District Court’s opinion and in our brief, Qualcomm maintained its monopoly through a brazen scheme carefully crafted and implemented over many years. This scheme consists of a web of anticompetitive conduct designed to allow Qualcomm to coerce customers, tilt the competitive playing field and exclude competitors, all the while shielding itself from legal scrutiny and capturing billions in unlawful gains.

The victims were Qualcomm’s own customers (original equipment manufacturers or OEMs), the long list of competitors it forced out of the modem chip market, including Intel, and ultimately consumers. 

Intel fought for nearly a decade to build a profitable modem chip business, and invested billions, hired thousands, acquired two companies and built innovative products that eventually made their way into Apple’s iPhones, including the most recently released iPhone 11. 

But when all was said and done, Intel could not overcome the artificial and insurmountable barriers to fair competition created by Qualcomm’s scheme and was forced to exit the market this year.

“As I have pointed out before, the District Court’s decision finding Qualcomm violated the antitrust laws comes on the heels of governmental entities around the globe reaching the same conclusion,” wrote Steven R. Rodgers is executive vice president and general counsel at Intel, in a post. “As a result of its anticompetitive practices, Qualcomm has been fined nearly $1 billion in China, $850 million in Korea, $1.2 billion by the European Commission and $773 million in Taiwan (later reduced in settlement). The FTC, however, did not seek monetary relief. Instead, it sought injunctive relief to prevent Qualcomm from continuing to engage in its unlawful conduct.”

Among other things, the District Court prohibited Qualcomm from continuing to implement the central component of its scheme, its coercive “no license, no chips” (NLNC) policy. Under the policy, Qualcomm cuts off handset OEMs’ purchases of modem chips unless they enter into a patent license agreement on Qualcomm’s terms. These onerous, one-sided terms enable Qualcomm to artificially lower the price of its modems while simultaneously inflating customers’ costs of using modem chips manufactured by competitors, like Intel, by charging royalties as large as the price of the modems themselves. 

The District Court concluded that the NLNC policy, together with other anticompetitive behavior on Qualcomm’s part, unlawfully distorted and, in fact, destroyed the competitive playing field.

The world benefits from fair competition in the wireless technology market. Given the importance of wireless technology to the future of connected computing, including the revolutionary promise of 5G, we strongly support the efforts of the FTC and other law enforcement agencies to require Qualcomm to obey the laws and compete on a level playing field.

“We hope our amicus brief will help in clarifying the full extent of the harm that Qualcomm’s unlawful behavior has caused and will continue to cause if left unchecked,” Stevans added.

Intel releases new class of AI hardware from cloud to edge to boost AI development, deployment and performance

Intel has updated its artificial intelligence (AI) offerings with new products designed to accelerate AI system development and deployment from cloud to edge. Intel demonstrated its Intel Nervana Neural Network Processors (NNP) for training (NNP-T1000) and inference (NNP-I1000) — Intel’s initial purpose-built ASICs for complex deep learning with incredible scale and efficiency for cloud and data center customers. 

Intel also revealed its next-generation Intel Movidius Vision Processing Unit (VPU) for edge media, computer vision and inference applications.

These products further strengthen Intel’s portfolio of AI solutions, which is expected to generate more than $3.5 billion in revenue in 2019. The broadest in breadth and depth in the industry, Intel’s AI portfolio helps customers enable AI model development and deployment at any scale from massive clouds to tiny edge devices, and everything in between.

Now in production and being delivered to customers, the new Intel Nervana NNPs are part of a systems-level AI approach offering a full software stack developed with open components and deep learning framework integration for maximum use.

The Intel Nervana NNP-T strikes the right balance between computing, communication and memory, allowing near-linear, energy-efficient scaling from small clusters up to the largest pod supercomputers. 

The Intel Nervana NNP-I is power- and budget-efficient and ideal for running intense, multimodal inference at real-world scale using flexible form factors. Both products were developed for the AI processing needs of AI customers like Baidu and Facebook.

“We are excited to be working with Intel to deploy faster and more efficient inference compute with the Intel Nervana Neural Network Processor for inference and to extend support for our state-of-the-art deep learning compiler, Glow, to the NNP-I,” said Misha Smelyanskiy, director, AI System Co-Design at Facebook.

Additionally, Intel’s next-generation Intel Movidius VPU, scheduled to be available in the first half of 2020, incorporates unique, highly efficient architectural advances that are expected to deliver leading performance — more than 10 times the inference performance as the previous generation — with up to six times the power efficiency of competitor processors. 

Intel also announced its new Intel DevCloud for the Edge, which along with the Intel Distribution of OpenVINO toolkit, addresses a key pain point for developers — allowing them to try, prototype and test AI solutions on a broad range of Intel processors before they buy hardware.

With most of the world running some part of its AI on Intel Xeon scalable processors, Intel continues to improve this platform with features like Intel Deep Learning Boost with Vector Neural Network Instruction (VNNI) that bring enhanced AI inference performance across the data center and edge deployments. 

While that will continue to serve as a strong AI foundation for years, the most advanced deep learning training needs for Intel customers call for performance to double every 3.5 months, and those types of breakthroughs will only happen with a portfolio of AI solutions like Intel’s. Intel is equipped to look at the full picture of computing, memory, storage, interconnect, packaging and software to maximize efficiency, programmability and ensure the critical ability to scale up distributing deep learning across thousands of nodes to, in turn, scale the knowledge revolution.

Mellanox Skyway 200 Gigabit HDR InfiniBand to Ethernet gateway appliance released for high performance and cloud data centers

Mellanox Technologies introduced Mellanox Skyway, a 200 gigabit HDR InfiniBand to Ethernet gateway appliance. Mellanox Skyway enables a scalable and efficient way to connect the high-performance, low-latency InfiniBand data center to external Ethernet infrastructures or connectivity.

Mellanox Skyway is the next generation of the existing 56 gigabit FDR InfiniBand to 40 gigabit Ethernet gateway system, deployed in multiple data centers around the world.

High performance computing, artificial intelligence, data-intensive and cloud infrastructures leverage InfiniBand's high data throughput, extremely low latency, and smart in-network computing acceleration engines to deliver critical application performance and scalability. 

For cases requiring connectivity into external Ethernet-based platforms, Mellanox offers the Skyway appliance, a 1.6 terabit-per-second InfiniBand to Ethernet gateway appliance, supporting eight 100 or 200 gigabit ports on each of the InfiniBand and Ethernet sides. IT managers can scale the number of Skyway appliances over time to meet the demands of their users.

By leveraging the Mellanox Skyway appliance, InfiniBand data centers can maintain their lowest interconnect latency to ensure maximum applications performance. Other non-Ethernet or proprietary network providers offer network-integrated or silicon-integrated gateways to Ethernet, which impose higher interconnect latency within the data center that can reduce the overall data center performance.