Intel releases new class of AI hardware from cloud to edge to boost AI development, deployment and performance

Intel has updated its artificial intelligence (AI) offerings with new products designed to accelerate AI system development and deployment from cloud to edge. Intel demonstrated its Intel Nervana Neural Network Processors (NNP) for training (NNP-T1000) and inference (NNP-I1000) — Intel’s initial purpose-built ASICs for complex deep learning with incredible scale and efficiency for cloud and data center customers. 

Intel also revealed its next-generation Intel Movidius Vision Processing Unit (VPU) for edge media, computer vision and inference applications.

These products further strengthen Intel’s portfolio of AI solutions, which is expected to generate more than $3.5 billion in revenue in 2019. The broadest in breadth and depth in the industry, Intel’s AI portfolio helps customers enable AI model development and deployment at any scale from massive clouds to tiny edge devices, and everything in between.

Now in production and being delivered to customers, the new Intel Nervana NNPs are part of a systems-level AI approach offering a full software stack developed with open components and deep learning framework integration for maximum use.

The Intel Nervana NNP-T strikes the right balance between computing, communication and memory, allowing near-linear, energy-efficient scaling from small clusters up to the largest pod supercomputers. 

The Intel Nervana NNP-I is power- and budget-efficient and ideal for running intense, multimodal inference at real-world scale using flexible form factors. Both products were developed for the AI processing needs of AI customers like Baidu and Facebook.

“We are excited to be working with Intel to deploy faster and more efficient inference compute with the Intel Nervana Neural Network Processor for inference and to extend support for our state-of-the-art deep learning compiler, Glow, to the NNP-I,” said Misha Smelyanskiy, director, AI System Co-Design at Facebook.

Additionally, Intel’s next-generation Intel Movidius VPU, scheduled to be available in the first half of 2020, incorporates unique, highly efficient architectural advances that are expected to deliver leading performance — more than 10 times the inference performance as the previous generation — with up to six times the power efficiency of competitor processors. 

Intel also announced its new Intel DevCloud for the Edge, which along with the Intel Distribution of OpenVINO toolkit, addresses a key pain point for developers — allowing them to try, prototype and test AI solutions on a broad range of Intel processors before they buy hardware.

With most of the world running some part of its AI on Intel Xeon scalable processors, Intel continues to improve this platform with features like Intel Deep Learning Boost with Vector Neural Network Instruction (VNNI) that bring enhanced AI inference performance across the data center and edge deployments. 

While that will continue to serve as a strong AI foundation for years, the most advanced deep learning training needs for Intel customers call for performance to double every 3.5 months, and those types of breakthroughs will only happen with a portfolio of AI solutions like Intel’s. Intel is equipped to look at the full picture of computing, memory, storage, interconnect, packaging and software to maximize efficiency, programmability and ensure the critical ability to scale up distributing deep learning across thousands of nodes to, in turn, scale the knowledge revolution.

Aldec delivers comprehensive portfolio of FMC daughter cards

Aldec Inc., vendor of mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, expanded its  FPGA Mezzanine Card (FMC) product line to support various applications in the areas of IIoT, networking, embedded vision and automotive.

The FMC standard from ANSI/VITA has been a key enabler for extending I/O support for a range of applications.

Established in 1984, Aldec provides electronic design certification and offers a patented technology suite including RTL Design, RTL simulators, hardware-assisted verification, SoC and ASIC prototyping, design rule checking, CDC verification, IP cores, high-performance computing platforms, embedded development systems, requirements lifecycle management, DO-254 functional verification and military/aerospace solutions. 

“We now provide the most comprehensive portfolio of FMC daughter cards that can be used for FPGA development, ASIC emulation and prototyping,” said Zibi Zalewski, hardware division general manager. “Our FMC connectors are based on High Pin Count (HPC) type that is compliant with ANSI/VITA 57.1, and provides individual signaling speed of up to 25 Gb/s per link and overall bandwidth of 200 Gb/s between the daughter card and carrier card for selected configurations.”

The FMC daughter cards are compatible with TySOM FPGA development boards or HES ASIC emulation/prototyping boards.

NTT Electronics contributes Goldstone - open source network OS for disaggregated coherent transponders to telecom infra project

NTT Electronics delivered on Wednesday its Goldstone Network Operating Software (NOS *1) for disaggregated coherent transponders to the Telecom Infra Project’s NOS Software Project hosted by the Open Optical and Packet Transport project group. Launched in February 2016, TIP was started with the goal of accelerating the pace of innovation in the telecom industry.

Goldstone utilizes many existing open source components which have been developed in Open Compute Project (OCP *2) and Telecom Infra Project (TIP *3) including Open Network Linux (ONL *4), SONiC *5, Switch Abstraction Interface (SAI *6) and Transponder Abstraction Interface (TAI *7) to provide a full-fledged open source solution. ONL is used as the base operating system and provides a wide range of open network device support. 

NTT Electronics (NEL) has been developing and commercializing optical communications devices since 1995. It has complete portfolio of optical and electronics products to cover the industry needs for 100G-and-beyond link systems, ROADM components and FTTH networks.

On top of ONL, Kubernetes *8 is employed to enable containerized application management, which realizes flexible and modular software composition. SONiC/SAI is deployed as a fleet of containers when the target hardware comprises Ethernet switch ASIC, whereas TAI is used when the target hardware has coherent transponder components. 

Due to its modular architecture, Goldstone can be extended to support networking devices, which don’t have Ethernet ASIC, but may include conventional transponders, ROADMs or amplifiers in the future.

Goldstone was originally started as a prototype NOS for Edgecore’s Cassini Platform by the proposal from NTT Electronics. This has led to a production deployment by mixi in Japan. 

More than five industry partners are using Goldstone for evaluation on the Cassini platform. It is also being incorporated in Wistron’s Galileo platform.

The NOS is planned to be contributed to TIP Open Optical Packet Transport (OOPT *9) group as an open source project. Goldstone is planned to be part of a live running demonstration at the TIP Summit 2019.

Fortinet’s FortiGate 60F sets new benchmark for security compute ratings; boosts performance for integrated security and SD-WAN

Fortinet announced the FortiGate 60F Next-Generation Firewall, its latest desktop secure SD-WAN appliance. With over 1.5 million units sold worldwide, the FortiGate 60 series is the best-selling next-generation firewall and now includes Fortinet’s purpose-built system on a chip 4 (SOC4) security processor to achieve the highest Security Compute Ratings in the industry to support customers’ WAN edge transformation.

Digital innovation and rapid cloud adoption is changing the face of today’s business and has created significant challenges for organizations, such as poor user experience due to network bandwidth constraints and increased security risks with branches connected to the internet. 

Software-defined wide area networks (SD-WANs) have emerged as the favored solution to solve these issues while also reducing the costs associated with MPLS connections. 

However, not all SD-WAN solutions have risen to the requirements of existing WAN edge. Many SD-WAN solutions on the market are incomplete and do not adequately provide the right performance, visibility, or security to ensure a secure connection and high quality of user experience.

To continue its focus on supporting enterprises’ WAN edge transformation and delivering Secure SD-WAN, Fortinet is announcing the latest next-generation firewall to include its patented SOC4 security processor - the FortiGate 60F. 

FortiGate 60F now consolidates SD-WAN, advanced routing, and advanced security capabilities into a single appliance that enables network leaders to deploy Secure SD-WAN, while reducing complexity by consolidating point products into a single offering. This allows high performance and improved user experience at an optimal total cost of ownership (TCO).
 

To help customers maintain high quality user experience for their business critical traffic (be it SaaS, multi-cloud, or unified communications), FortiGate 60F delivers ideal application steering, giving visibility to all traffic (even if encrypted) without impacting performance and ensuring all critical applications are routed to their best path.
 

FortiGate 60F leverages Security-Driven Networking principals – powered by Fortinet’s patented SOC4 security processor – to deliver the fastest deep inspection of SSL/TLS encrypted traffic (including the industry’s first support for TLS 1.3) at 750Mbps, 11 times greater than the industry average. 

The FortiGate 60F offers comprehensive threat prevention with IPS, application control, and anti-malware at 700Mbps, four times greater than the industry average, to help customers protect their network without impacting performance.

Fortinet security processors radically increase the performance, scalability, and value of Fortinet solutions while greatly improving user experience and shrinking space and power requirements. Security Compute Rating is a benchmark that compares the performance of Fortinet’s purpose-built ASIC-based next-generation firewall appliance to other NGFW and SD-WAN vendors in that same price range that utilize generic CPUs for networking and security capabilities. 

“We hear from an increasing number of customers who are struggling to achieve the required level of user experience, visibility, and security at their WAN edge to support key business applications,” said John Maddison, EVP of Products and CMO at Fortinet. “With today’s introduction of the FortiGate 60F powered by our latest security processor, Fortinet continues its commitment to security innovation, setting industry records for performance to empower network leaders to truly transform their WAN edge.”

Renesas expands access of IP solutions including 7nm process TCAM, advanced standard Ethernet TSN IPs

Renesas Electronics announced expanded access to its highly sought portfolio of intellectual property (IP) licenses that allow designers to meet a broad range of customer requirements in a rapidly changing industry. Starting today, customers will have access to IPs such as advanced 7nm (nanometer) SRAM and TCAM, and standard Ethernet time-sensitive networking (TSN) IP. 

Furthermore, Renesas is working on providing a system IP which includes PIM (processing in memory), which attracted attention as an AI accelerator, presented in a conference paper in June 2019. With these IPs, customers can jump start their advanced semiconductor device development projects, such as the development of next-generation artificial intelligence (AI) chips or ASICs for 5G networks.

The Renesas accelerator is based on the processing-in-memory (PIM) architecture, an increasingly popular approach for AI technology, in which multiply-and-accumulate operations are performed in the memory circuit as data is read out from that memory.

Customers developing custom chips or using FPGA devices for early development can leverage Renesas IP in their subsystem design or speed up software development, respectively, allowing them to focus resources on their speciality areas, speed up the development process, and bring highly competitive products to market. 

Customers who prefer to use existing software assets can take advantage of Renesas IP assets to achieve more efficient system development by reducing the resources required to develop, verify, and evaluate software and boards.

To support customers’ semiconductor development efforts, Renesas has also established a network of partner companies ready to support users' unique needs. This network includes design houses that perform contract semiconductor design and technology partners who will provide an array of software and middleware tools. 

This network will accelerate users' technology innovations and product development efforts by lowering the barriers to entry for semiconductor device and FPGA development. Renesas can also introduce experienced users to model-based design development environments that fully utilize leading-edge IP.

In September 2018, Renesas opened its extensive IP license portfolio, offering access to more than 40 licenses, including CPU cores, timer IP for motor applications, USB cores, and SRAM. In 2019, Renesas received over 100 enquiries and have started supplying IPs to many users. Renesas aims to exceed IP sales annual market growth rate of 10 percent, and will expand the provision of IP and support system while creating new, and expanding old, IP markets.