Toshiba advances next generation ADAS that uses Cypress Semper fail-safe storage

Cypress Semiconductor announced Wednesday that Toshiba Electronic Devices & Storage Corporation has selected Cypress’ Semper NOR Flash for its next-generation Visconti line of automotive Advanced Driver Assistance Systems (ADAS). 

Architected with an embedded Arm Cortex-M0 processing core, the Semper family is purpose-built for demanding automotive environments where high-density and functional safety compliance are required. The Toshiba Visconti ADAS SoC is specifically targeted for key automobile makers working toward Autonomous Driving level 2.

The Cypress Semper NOR Flash family leads the industry in Functional Safety compliance and was the first flash to be designed specifically to meet the ISO26262 automotive functional safety standard, reaching ASIL-B compliancy. 

Semper NOR Flash also supports automotive temperatures up to +125°C (AEC-Q100 Grade 1) and meets the density and performance requirements for storage in ADAS applications through Autonomous Driving level 5.

“For the Toshiba Visconti5 ADAS SoC, it is critical that the integrated components selected for the design are field-proven, built to the highest standards of safety and reliability, and will have the endurance required for advanced ADAS applications,” said Takeshi Sugahara, Technology Executive of Toshiba Electronic Devices & Storage Corporation. “Cypress’ fail-safe storage solutions are a key to enable our Visconti5 platform to exceed our customers’ expectations and requirements for next-generation automotive designs.”

“Cypress is proud of its success in providing the world’s most advanced and reliable fail-safe storage products with integrated compute core and functional safety for automotive applications,” said Amr El-Ashmawi, vice president of marketing, Memory Products Division at Cypress. “As the world’s number one market share provider of automotive-grade flash, we look forward to continuing our collaborative work with Toshiba for delivering next-generation ADAS systems in this growing segment of the automotive market.”

Everspin achieves data center OEM qualification of its 1Gb STT-MRAM offering; announces production shipments

Everspin Technologies announced on Wednesday that it has secured the qualification notice from a major server OEM of its 1-Gigabit (Gb) Spin-transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) device. This qualification notice affirms the quality, performance and specifications of the 1Gb device and enables its use in the production of products for this customer. 

The STT-MRAM provides a significant reduction in switching energy compared to Toggle MRAM, and is highly scalable, enabling higher density memory products. Everspin’s third generation of MRAM technology uses a Perpendicular MTJ, and has developed materials and Perpendicular MTJ stack designs with high perpendicular magnetic anisotropy, which provides long data retention, small cell size, greater density, high endurance and low power.

The 1Gb is the newest generation of STT-MRAM, utilizing ST-DDR4 which is a JEDEC-like DDR4 interface with some modifications needed to take advantage of the persistence from MRAM technology. These products perform like a persistent DRAM but with no refresh required. Additional products are planned which will utilize high speed serial interfaces for a range of embedded applications.

Earlier this summer, Everspin announced pilot manufacturing of its 28 nm 1Gb device and is now qualified to make production shipments to its first qualifying customer. 

No other manufacturer has achieved production of any discrete STT-MRAM device, a further testament to Everspin’s position in the field having achieved production of its 256Mb STT-MRAM in 2017. To date, Everspin has produced more than 120 million units of its Toggle and STT-MRAM devices.

Everspin’s STT-MRAM devices allow enterprise infrastructure and data center providers to increase the reliability and performance of systems where low latency data persistence is critical. This is achieved by delivering protection against power loss and allowing storage OEMs to significantly improve quality of service of their products. 

Similar benefits can also be achieved using the 1Gb STT-MRAM device as a persistent data write buffer in storage and fabric accelerators, computational storage, and other applications.

The data center OEM name is not being disclosed as they have not yet announced their end product(s).

“We continue to make great strides in the commercialization of MRAM across many market segments, including the data center,” said Kevin Conley, president and CEO of Everspin. “It is very rewarding to see the completion of this very important customer milestone with our 1Gb STT-MRAM, along with the collaboration that has taken place with our customers and our ecosystem partners.”

Kioxia introduces Twin BiCS FLASH, its 3D semicircular flash memory cell structure that helps boost bit density

Kioxia announced development of the initial three-dimensional (3D) semicircular split-gate flash memory cell structure “Twin BiCS FLASH” using specially designed semicircular Floating Gate (FG) cells. Twin BiCS FLASH achieves superior program slope and a larger program/erase window at a much smaller cell size compared to conventional circular Charge Trap (CT) cells. 

These attributes make this new cell design a promising candidate to surpass four bits per cell (QLC) for significantly higher memory density and fewer stacking layers. This technology was announced at the IEEE International Electron Devices Meeting (IEDM) held in San Francisco, California.

3D flash memory technology has achieved high bit density with low cost per bit by increasing the number of cell stacked layers as well as by implementing multilayer stack deposition and high aspect ratio etching. In recent years, as the number of cell layers exceeds 100, managing the trade-offs among etch profile control, size uniformity and productivity is becoming increasingly challenging. 

To overcome this problem, Kioxia developed a new semicircular cell design by splitting the gate electrode in the conventional circular cell to reduce cell size compared to the conventional circular cell, enabling higher-density memory at a lower number of cell layers.

The circular control gate provides a larger program window with relaxed saturation problems when compared with a planar gate because of the curvature effect, where carrier injection through the tunnel dielectric is enhanced while electron leakage to the block (BLK) dielectric is lowered. In this split-gate cell design, the circular control gate is symmetrically divided into two semicircular gates to take advantage of the strong improvement in the program/erase dynamics. 

The conductive storage layer is employed for high charge trapping efficiency in conjunction with the high-k BLK dielectrics, achieving high coupling ratio to gain program window as well as reduced electron leakage from the FG, thus relieving the saturation issue. The experimental program/erase characteristics reveal that the semicircular FG cells with the high-k-based BLK exhibit significant gains in the program slope and program/erase window over the larger-sized circular CT cells. 

The semicircular FG cells, having superior program/erase characteristics, are expected to attain comparably tight QLC Vt distributions at small cell size. Further, integration of low-trap Si channel makes possible more than four bits/cell, e.g., Penta-Level Cell (PLC). These results confirm that semicircular FG cells are a viable option to pursue higher bit density.

Going forward, Kioxia’s research and development efforts aimed at innovation in flash memory will include continuing Twin BiCS FLASH development and seeking its practical applications.

KIOXIA’s KumoScale software now put on UNH-IOL NVMe-oF integrator’s list

KIOXIA America (formerly Toshiba Memory America), the U.S.-based subsidiary of KIOXIA Corp., announced this week that its KumoScale storage software with NVM Express over Fabrics (NVMe-oF) v3.11 has been added to The University of New Hampshire InterOperability Laboratory’s (UNH-IOL) official Integrator’s List. 

In order to be considered for inclusion on the list, technologies must undergo conformance testing performed by the UNH-IOL through laboratory tests or during an NVMe plugfest. Successful completion of this testing provides a level of assurance that the product being tested will function properly in NVMe-oF environments.

Developed with a strong focus on virtualizing, managing and securing data, the KumoScale software suite provides a feature-rich storage abstraction for containers and virtual machines. It delivers secure flash access, API access to orchestration frameworks, among other capabilities, and takes advantage of the unique performance characteristics of NVMe SSDs. 

KumoScale software was the first storage software technology to be granted NVMe-oF certification by the UNH-IOL, and KIOXIA America continues to submit new releases of the software suite for certification. 

“Ensuring the interoperability of technologies with the NVMe standards is at the heart of what we do,” noted David Woolf, senior engineer, Datacenter Technologies, UNH-IOL. “KumoScale block storage software was the first of its kind to be listed on the NVMe-oF Integrator’s List back in 2017. We commend KIOXIA for their continued software innovations and for making NVMe-oF more deployable in cloud data centers.”

PAC Storage enhances data storage performance with scale-out NAS, latest controllers, and 32Gb FC / 25GbE connectivity

PAC Storage (PAC) has announced three latest enhancements to their existing line of hardware: scale-out NAS systems, next generation controllers, and 32Gb FC and 25GbE host boards. Each enhancement dramatically accelerates system performance, providing tremendous benefits to a variety of industries and applications including database, analytics, virtualization, motion media, file sharing, cloud data integration, data science and AI.

The all-new Scale-Out NAS systems product line supports 100+ Gbps performance and scaling to more than 100 PB capacity. These solutions allow capacity and performance to be increased by horizontally adding another node (array) to the system.

PAC Storage is an enterprise data storage hardware solution. Since 2005, PAC SAN solutions have been data center cornerstones nationwide for primary, secondary, backup, and disaster recovery. In 2017, PAC introduced PS storage solutions which offer SAN and NAS, and include cloud gateway options. Offering the ideal price point, PAC feature-rich solutions are renowned for no single point of failure and scalability to petabytes of on-premise storage.

These scale-out NAS systems are joined by new Next Generation Controllers featuring up to twelve cores of the latest Intel CPU technology. Improvements also include doubling the controller cache to 512GBs, enabling PAC controllers to now boost performance by up to 80 percent, fulfilling the demanding requirements of today’s intensive enterprise data environments. 

Both PAC Storage PS and PAC All Flash product lines will feature the next generation controllers with all flash designed to deliver optimal SSD performance and response times of less than 0.35 milliseconds, as well as up to 900K IOPS and 10,000/5,500 MB/s read/write speed.

PAC Scale-Out NAS supports adding more nodes achieving more performance and capacity via a clustered system with up to 100 plus GBps read/write speed and more then a 100PBs of storage for the needs of future data growth.   

PAC also supports auto-balancing function that supports distribution of data across all nodes in the system. When a large number of users access data simultaneously, the system share the workload through parallel processing, solving the problem of a single node performance limitation and improving the access e­­fficiently.  

To prevent critical data loss and ensure continuous storage services PACs Scale-Out system is designed with the support of multi-layer data protection on hard drives, notes, and cluster levels. If any of the elements fails, neither the data will be lost nor the performance will be affected.  

If a single node failure is detected, PAC initiates self-healing function to recover the data from the faulty node. On a cluster level, users can use the Rsync feature for remote backup of the cluster file to remote cluster or remote NAS.   

Rounding out the new PAC Storage enhancements are 32Gb FC and 25GbE host boards which enable enterprise customers to migrate to the new networking standards for data access acceleration. The 32Gb FC and 25GbE host connectivity more than double system bandwidth via a single lane, making the storage infrastructure more scalable and flexible. 

"With this solution, we’ve truly hit it out of the park,” said PAC CEO Rick Crane. “The new scale-ut version of NAS is an outstanding and innovative alternative for our Isilon customers looking for a scale-out environment that’s simple to administer and easy on their budget. Even better, they can take advantage of the Next Generation technology in this product, as well as in our existing portfolio of SAN/NAS."

Samsung secures global recognition for environmental sustainability of its semiconductor offerings

Samsung Electronics announced that its 512-gigabyte (GB) embedded Universal Flash Storage (eUFS) 3.0 will be awarded Carbon Footprint and Water Footprint Certifications from UK-based Carbon Trust. 

Samsung’s 512GB eUFS 3.0 is initial mobile memory in the industry to be recognized by an international certifying organization, which was made possible through the company’s extensive efforts to reduce carbon and water footprints.

The Carbon Trust is a globally accredited non-profit certification body established by the British government to accelerate the move to a sustainable, low-carbon economy. Each certification by the Carbon Trust was made after a thorough assessment of the environmental impact of carbon emissions and water usage before and throughout the production cycle, based on international standards.

Based on the company’s fifth-generation (90+ layers) V-NAND, Samsung’s 512GB eUFS 3.0 provides optimal speed, power efficiency and productivity to deliver twice the capacity and 2.1 times the sequential speed of its fourth generation (64 layers) V-NAND-based 256GB eUFS 2.1, while requiring 30 percent less operating voltage. 

Samsung’s 512GB eUFS 3.0 stacks eight of the company’s fifth-generation 512-gigabit (Gb) V-NAND die and integrates a high-performance controller. At 2,100 megabytes-per-second (MB/s), the new eUFS doubles the sequential read rate of Samsung’s latest eUFS memory (eUFS 2.1) which was announced in January this year. 

The offering’s blazing read speed is four times faster than that of a SATA solid state drive (SSDs) and 20 times faster than a typical microSD card, allowing premium smartphones to transfer a full HD movie to a PC in about three seconds. In addition, the sequential write speed also has been improved by 50 percent to 410MB/s, which is equivalent to that of a SATA SSD.

Additionally, Samsung’s fifth-generation V-NAND utilizes a unique etching technology that pierces more than 90 cell layers in a single precise step. This allows the chip to have nearly 1.5 times more stacked layers than the previous generation and accommodate a 25-percent reduction in chip size. Such innovations help to minimize the overall increase in carbon and water footprints for each V-NAND cell layer.

Samsung is also being awarded Environmental Product Declaration (EPD) labels for its ‘1-terabyte (TB) eUFS 2.1’ and its ‘fifth-generation 512-gigabit (Gb) V-NAND’ by the Korean Ministry of Environment.

Samsung plans to actively expand the adoption of its highly sustainable, high-capacity premium memory solutions into many more flagship smartphones and further strengthen global partnerships for its next-generation memory technologies.

“We are extremely pleased that our cutting-edge memory technologies not only demonstrate our capability to overcome more challenging process complexities, but also are recognized for their environmental sustainability,” said Chanhoon Park, executive vice president and head of Giheung Hwaseong Pyeongtaek Complex at Samsung Electronics. “Samsung will continue to create memory solutions that provide the highest levels of speed, capacity and power efficiency at extremely small geometries for end-users worldwide.”

NVIDIA releases Magnum IO software line to help reduce data bottlenecks for data scientists and AI, HPC researchers

NVIDIA introduced NVIDIA Magnum IO, a suite of software to help data scientists and AI and high performance computing researchers process massive amounts of data in minutes, rather than hours. This offering ahs been developed in close collaboration with vendors in networking and storage, including DataDirect Networks, Excelero, IBM, Mellanox and WekaIO.

Optimized to eliminate storage and input/output bottlenecks, Magnum IO delivers up to 20 times faster data processing for multi-server, multi-GPU computing nodes when working with massive datasets to carry out complex financial analysis, climate modeling and other HPC workloads.

At the heart of Magnum IO is GPUDirect, which provides a path for data to bypass CPUs and travel on “open highways” offered by GPUs, storage and networking devices. Compatible with a wide range of communications interconnects and APIs — including NVIDIA NVLink and NCCL, as well as OpenMPI and UCX — GPUDirect is composed of peer-to-peer and RDMA elements.

Its newest element is GPUDirect Storage, which enables researchers to bypass CPUs when accessing storage and quickly access data files for simulation, analysis or visualization.

Magnum IO integrates infrastructure elements to maximize storage and network I/O performance and functionality. It optimizes IO performance by bypassing the CPU to enable direct IO between GPU memory and network storage. It also relieves CPU contention to create a more balanced GPU-accelerated system and delivers peak IO bandwidth with up to ten times fewer CPU cores, and provides optimized implementation for current and future platforms, whether the data transfers are latency sensitive, bandwidth sensitive, or collectives.

NVIDIA Magnum IO software is available, with the exception of GPUDirect Storage, which is currently available to select early-access customers. Broader release of GPUDirect Storage is planned for the first half of next year.

Supermicro aligns with Intel to offer large scale distributed training AI systems to meet needs of deep learning training models

Super Micro Computer is collaborating with Intel on AI solutions that are validated on the Intel Nervana Neural Network Processor for Training (NNP-T). Intel's NNP-T is a purpose-built AI training ASIC supporting the growing compute needs of deep learning training models.

The Intel Nervana NNP-T solves memory constraints and is designed to scale out through systems with racks easier than today's solutions. As part of the validation process, Supermicro integrated 8 NNP-T processors, dual 2nd Generation Intel Xeon scalable processors, up to 6TB DDR4 memory per node supporting both PCIe card and OAM form factors. Supermicro NNP-T systems are expected to be available mid-year 2020.

With high compute utilization and high-efficiency memory architecture for complex deep learning models, the Supermicro NNP-T AI System is built to validate two key real-world considerations: accelerating the time to train ever-complex AI models and doing it within a given power budget. The system enables faster AI model training with images and speech, more efficient gas & oil exploration, more accurate medical image analytics, and faster autonomous driving model generation.

"Supermicro is excited to cooperate with Intel for the Nervana NNP-T platform," said Charles Liang, president, and CEO of Supermicro. "Striking a balance among computing, communication, and memory, the validated NNP-T ASICs on Supermicro systems can train large AI models with near-linear scaling efficiency via intra- and inter-chassis links."

"Supermicro has validated our Deep Learning (DL) solution and is helping us prove the Nervana NNP-T system architecture, including card and server design, interconnect, and rack," said Naveen Rao, corporate vice president and general manager, Artificial Intelligence Products Group, Intel.

Intel releases new class of AI hardware from cloud to edge to boost AI development, deployment and performance

Intel has updated its artificial intelligence (AI) offerings with new products designed to accelerate AI system development and deployment from cloud to edge. Intel demonstrated its Intel Nervana Neural Network Processors (NNP) for training (NNP-T1000) and inference (NNP-I1000) — Intel’s initial purpose-built ASICs for complex deep learning with incredible scale and efficiency for cloud and data center customers. 

Intel also revealed its next-generation Intel Movidius Vision Processing Unit (VPU) for edge media, computer vision and inference applications.

These products further strengthen Intel’s portfolio of AI solutions, which is expected to generate more than $3.5 billion in revenue in 2019. The broadest in breadth and depth in the industry, Intel’s AI portfolio helps customers enable AI model development and deployment at any scale from massive clouds to tiny edge devices, and everything in between.

Now in production and being delivered to customers, the new Intel Nervana NNPs are part of a systems-level AI approach offering a full software stack developed with open components and deep learning framework integration for maximum use.

The Intel Nervana NNP-T strikes the right balance between computing, communication and memory, allowing near-linear, energy-efficient scaling from small clusters up to the largest pod supercomputers. 

The Intel Nervana NNP-I is power- and budget-efficient and ideal for running intense, multimodal inference at real-world scale using flexible form factors. Both products were developed for the AI processing needs of AI customers like Baidu and Facebook.

“We are excited to be working with Intel to deploy faster and more efficient inference compute with the Intel Nervana Neural Network Processor for inference and to extend support for our state-of-the-art deep learning compiler, Glow, to the NNP-I,” said Misha Smelyanskiy, director, AI System Co-Design at Facebook.

Additionally, Intel’s next-generation Intel Movidius VPU, scheduled to be available in the first half of 2020, incorporates unique, highly efficient architectural advances that are expected to deliver leading performance — more than 10 times the inference performance as the previous generation — with up to six times the power efficiency of competitor processors. 

Intel also announced its new Intel DevCloud for the Edge, which along with the Intel Distribution of OpenVINO toolkit, addresses a key pain point for developers — allowing them to try, prototype and test AI solutions on a broad range of Intel processors before they buy hardware.

With most of the world running some part of its AI on Intel Xeon scalable processors, Intel continues to improve this platform with features like Intel Deep Learning Boost with Vector Neural Network Instruction (VNNI) that bring enhanced AI inference performance across the data center and edge deployments. 

While that will continue to serve as a strong AI foundation for years, the most advanced deep learning training needs for Intel customers call for performance to double every 3.5 months, and those types of breakthroughs will only happen with a portfolio of AI solutions like Intel’s. Intel is equipped to look at the full picture of computing, memory, storage, interconnect, packaging and software to maximize efficiency, programmability and ensure the critical ability to scale up distributing deep learning across thousands of nodes to, in turn, scale the knowledge revolution.